In semiconductor manufacturing and during the fabrication of a transistor gate, a spacer material is conformally applied to the transistor gate, and then partially removed to form a sidewall spacer on a sidewall of the transistor gate. During the partial removal of the spacer material from the transistor gate and the substrate, the success of a spacer etch process is determined by measuring, among other things, the following performance metrics: (a) the size of the sidewall spacer footing, (b) the depth of the substrate recess, (c) the amount of sidewall spacer critical dimension (CD) slimming, and (d) the depth of the spacer top recess. Conventional spacer etch processes produce unacceptable results in at least one of these performance metrics.
Furthermore, as the dimensions of the transistor gate continue to shrink, the fringe capacitance between the gate and contact, as well as between the gate and facet of the source/drain (S/D), has increased. To counter this increase in fringe capacitance, low-k dielectric materials have been implemented as the spacer material. Therefore, the success of the spacer etch process is also determined by measuring the effect of the spacer etch process on the resultant dielectric constant of the low-k dielectric material used for the spacer material. Conventional spacer etch processes deplete the spacer material of various constituents, which in turn, causes an undesirable increase in the dielectric constant.